In a conventional Low Temperature Poly-Silicon (LTPS) shift register unit, D flip-flops consisted of inverters and transmission gates are adopted. In generally, the conventional LTPS shift register unit includes two D flip-flops. In the LTPS shift unit, an output signal is latched by the D flip-flop, and shift and transmission of the signal are controlled by a clock signal.
FIG. 1 illustrates a representative structure of the conventional LTPS shift register unit. As illustrated in FIG. 1, in the LTPS shift register unit, a first D flip-flop is consisted of a transmission gate TG1, a NAND gate Nand1, an inverter INV1 and a transmission gate TG2, and a second D flip-flop is consisted of a transmission gate TG3, a NAND gate Nand2, an inverter INV2 and a transmission gate TG4. When a clock signal CLK is of a low level and a reverse clock signal CLKB is of a high level so that the first D flip-flop is turned on, a signal outputted by a previous shift register unit enters into the first D flip-flop. At this time, the transmission gate TG3 at a front end of the second D flip-flop is in an OFF state, and thus the signal outputted by the NAND gate Nand1 cannot enter into the second D flip-flop. On the other hand, when the clock signal CLK is of a high level and the reverse clock signal CLKB is of a low level so that the transmission gate TG1 in the first D flip-flop is turned off, the state of the D flip-flop in a previous clock period is latched by the first D flip-flop. In other words, when the clock signal CLK is of a high level and the reverse clock signal CLKB is of a low level, the first D flip-flop latches the signal outputted by the first D flip-flop when the clock signal CLK is of the low level and the reverse clock signal CLKB is of the high level. At this time, the transmission gate TG3 in the second D flip-flop is turned on, and the signal outputted by the first D flip-flop enters into the second D flip-flop which then outputs this signal. Thus, a shift operation of the signal from a previous shift register unit to a next shift register unit is implemented. When the shift register unit operates, a reset signal RST is of a high level.
However, for the display apparatus, each shift register unit is used only once during a time period for displaying one frame of image. For example, in the display apparatus, if there are N rows of pixels and the time period for displaying one frame of image is T seconds, then one shift register unit may be used for merely T/N seconds during the time period for displaying one frame of the image. That is, during the time period for displaying one frame of image, each shift register unit is kept in an operation state for merely T/N seconds, but in a non-operation state for T−T/N seconds. In other words, during the time period of one frame, an operation period of each shift register unit is only T/N seconds, and a non-operation period thereof is T−T/N seconds.
In the conventional shift register unit, turning on and off of all the transmission gates are controlled by the clock signal CLK and the reverse clock signal CLKB. Even during a non-operation period, the transmission gates are still turned on and off by the clock signal CLK and the reverse clock signal CLKB. Each of the transmission gates is consisted of parallel connected complementary transistors. When the transmission gates are controlled to be turned on and off by the clock signal CLK and the reverse clock signal CLKB, the clock signal CLK and the reverse clock signal CLKB is required to be inputted to gate electrodes of the transistors. In each of the transistors, the gate electrode covers a gate insulation layer, which covers a substrate. Thus, a capacitor is formed between the gate electrode and the substrate, which may be called a gate capacitor. In this manner, the gate capacitor of the transistor will be charged by the signal inputted to the gate electrode of the transistor when the signal is of a high level, and will be discharged by the signal when the signal is of a low level. As a result, during the non-operation period, such charging and discharging of the circuit may cause meaningless power consumption. A contemporary display apparatus often includes hundreds or thousands stages of shift register units, and only one stage of the shit register unit circuit is operating at a same time, meanwhile the other shift register units are in the non-operation state. At this time, both the clock signal CLK and the reverse clock signal CLKB will be inputted to the transmission gates of the transfer register units which are in the non-operation state, which may cause meaningless but large power consumption.
It can be seen from above that, due to the fact that the transmission gates in the conventional shift register units are controlled to switch between being-turned-on and being-turned-off by the two complementary and reversed clock signals during the non-operation period, the gate capacitors of the transistors in the transmission gates are charged and discharged during the non-operation period, which causes meaningless but large power consumption.